There are a number of circuits that require a reference voltage that is lower than the supply voltage VDD. As one example, FIG. 15 shows the application of a clamp circuit 1502 in a circuit 1500 for reading data from word lines 1504 of a memory cell array 1503. During the read operation of the memory cell array 1503, the clamp circuit 1502 provides the reference voltage for the WL (word line) drivers 1506 to read a selected one of the word lines 1504. The clamp circuit 1502 controls the reference voltage of the WL driver 1506 so that the voltage applied to the WL driver 1506 behaves within the allowed operation window of the WL driver 1506.
Band gap references are not suitable for use as a read voltage because of the long response time (typically greater than 500 ns). Common conventional clamp circuits used as a read voltage reference include either a diode or PNP transistor to function as the clamp.
The basic functioning of a clamp circuit is discussed with reference to FIG. 1, which illustrates a conventional clamp circuit 100 employing a diode 106 as the clamp. A power supply 102 is connected via a resistance 104 to a point 107 at which it is desired to maintain a reference potential VREF. The point 107 is connected to ground 110 by the diode 106. In operation, whenever the potential at point 107 starts to rise above the potential VREF, the diode 106 starts to conduct such that the point 107 is connected to point 110 by a very low resistance, thus tending to maintain the potential at the point 107 at VREF. In practice, one or more PNP transistors are employed as the diode 106. A major disadvantages of a diode clamp circuit such as that illustrated in FIG. 1 is the strong temperature dependency of the current-voltage (IV) characteristics of the diode 106. This strong temperature dependency translates to insufficient clamp at high and low temperatures. FIG. 2A shows the IV-characteristics of a clamp circuit employ three PNP transistors in series as the diode 106, and FIG. 2B shows the voltage clamp characteristics of the three PNP transistors in series. It can be seen from FIGS. 2A and 2B that the reference voltage of the clamp circuit employing three PNP transistors in series as the diode is too high at low temperatures and also is too low at high temperatures. At very low temperatures (e.g., at 45.degree. C.), the circuit 100 exhibits virtually no clamp characteristics at all.
Using an NMOS transistor as a clamp device is not seen as being practical, because the gate should bias at a voltage range greater than the reference voltage, which is more difficult to control under different conditions such as temperature.
What is desired is a clamp circuit that operates substantially consistently over a wide temperature range.